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#riscv

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Benjamin Carr, Ph.D. 👨🏻‍💻🧬

#Debian13.0 Ready To Introduce Formal #RISCV Support But Still Bound By Slow Hardware
#Debian's RISC-V ambitions date back a decade when thfirst #RISCV64 port was started for Debian and then after all the work over the years, Debian 13.0 in August will finally debut it as an official architecture. #RV64GC is the current target for Debian RISC-V and using UEFI-based booting as the default. Over seventeen thousand source Debian packages are building for RISC-V with Trixie.
phoronix.com/news/Debian-13-RI

www.phoronix.comDebian 13.0 Ready To Introduce Formal RISC-V Support But Still Bound By Slow HardwareWith the Debian 13.0 release planned for 9 August, one of the notable fundamental features with this Debian 'Trixie' release is now supporting RISC-V as an official CPU architecture
Benjamin Carr, Ph.D. 👨🏻‍💻🧬

#NVIDIA Bringing #CUDA To #RISCV
NVIDIA's drivers and CUDA software stack are predominantly supported on x86_64 and AArch64 systems but in the past was supported on IBM POWER. This week at the RISC-V Summit China event, NVIDIA's Frans Sijstermans announced that CUDA will be coming to RISC-V.
#AMD for their part with the upstream #opensource #AMDKFD kernel compute driver can already build on RISC-V and the #ROCm user-space components can also be built on RISC-V.
phoronix.com/news/NVIDIA-CUDA-

www.phoronix.comNVIDIA Bringing CUDA To RISC-VNVIDIA announced this week that they are bringing their CUDA software to RISC-V processors.
𝕽𝖚𝖆𝖎𝖉𝖍𝖗𝖎𝖌𝖍

RISC-V and micro kernel synergy

midwest.social/post/31797421

midwest.socialRISC-V and micro kernel synergy - midwest.socialcross-posted from: https://midwest.social/post/31797333 [https://midwest.social/post/31797333] > I came across the post about Milk-V Titan [https://milkv.io/titan], and there was a comment asking about the lack of the V extension would hinder running Ubuntu 25.10 which was targetting a particular RISC-V configuration, and it made me wonder if there were an opportunity for micro kernels to exploit. > > Now, up-front: it’s been literally decades since I had an OS design class, and my knowledge of OS design is superficial; and while I’ve always been interested in RISC architectures, the depth of my knowledge of that also dates back to the 90’s. In particular RISC-V’s extension design approach is really, really shallow. It’s all at a lower level than I’ve concerned myself with for years and years. So I’m hoping for an ELI-16 conversation. > > What I was thinking was that a challenge of RISC-V’s design is that operating systems can’t rely on extensions being available, which (in my mind) means either a lot of really specific kernel builds – like, potentially an exponential number – or a similar number of code paths in the kernel code, making for more complicated and consequently more buggy kernels (per the McConnell rule). It made me wonder if this is not, then, an opportunity for micro kernels to shine, by exploiting an ability to load extension-specific modules based on a given CPU capability set. > > As I see it, the practicality of this depends on whether the extensions would be isolatable to kernel modules, or whether (like the FP extension) it’d just be so intrinsic that even the core kernel would need to vary. Even so, wouldn’t having a permutation of core kernel builds be smaller, more manageable, and less bug-prone than permutations of monolithic kernels? > > Given the number of different possible RISC-V combinations, would a micro kernel design not have an intrinsic advantage over monolithic kernels, and be able to exploit the more modular nature of their design?
#riscv
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Paolo Amoroso

Asm Editor is a web app IDE for learning, developing, and running x86, M68K, RISC-V, and MIPS Assembly code. It features an editor, assembler, and debugger, as well as other tools and learning resources.

asm-editor.specy.app

github.com/Specy/asm-editor

asm-editor.specy.appAsm EditorWrite, learn and run M68K, MIPS, RISC-V and X86 assembly code in your browser. View registers and memory, step and undo the execution.
#x86#m68k#mips
Jure Repinc

Milk-V Titan (RISC-V MINI-ITX, powered by UltraRISC UR-DP1000)

lemmy.ml/post/33274510

lemmy.mlMilk-V Titan (RISC-V MINI-ITX, powered by UltraRISC UR-DP1000) - Lemmy8 High-Performance RISC-V Cores UR-CP100 (up to 2.0GHz) * 1 Cluster (4x UR-CP100 cores) sharing 4MB, total 8MB * System-level cache: 16MB shared by 2 cluster (8 cores) The Most Powerful RISC-V Core in Mass Production to Date - UR-CP100 (RV64GCBHX) * 64-bit out-of-order 4-issue superscalar microarchitecture * SPECCPU2006 single-core INT@10.4/GHz * SPECCPU2006 single-core FP@12/GHz * UltraRISC proprietary high-performance “X” instruction set extension Compliant with RISC-V International Foundation Standards * Fully Compliant with RVA22 * Compliant with RVA23* (excluding “V” extension) Supports DDR4 Memory Stick, Up to 64GB * Compatible with standard PC-grade memory stick (UDIMM) * Supports standard DDR4 JEDEC JESD79-4A protocol * Supports maximum speed of 3200MT/s * Supports ECC Supports UEFI Boot * Supports ACPI, CPPC, SMBIOS * Standardized boot support * Native ISO file mounting * More flexible boot options * Enhanced security Supports Commodity NVMe SSDs (PCIe Gen4 4-lane) Supports High-Speed USB3 5Gbps Onboard Full-Size PCIe Connector with PCIe Gen4 16-lane
#riscv
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Dimly Lit Corners

#Goals2025

Moving away from the constant upgrade cycle & moving closer to the ideals of #PermaComputing #MalleableSoftware

Design and setup a redundant system of old/used, cheap, low-power devices running ia: #Guix, #Linux, #FreeBSD, #macOS, #HaikuOS, #Plan9Front, #X11, #P9, #NFS, all working together

Become an expert on #MicroControllers #ESP32 #STM32 #RP2040 #MIPS #RiscV

DIY sensors which sing like birds to communicate their status

DIY robots "drones"

Move as much as possible of my computing needs to the #Terminal, #Emacs, #Rio #CLI #TUI #P9

Get an #3DPrinter and learn to use it

Design and build my own portable 8dot #braille terminal & try out if 3x3 or 3x4 dots is also workable.

Design and build my own low-power computers, their OS, and tools

Writing more of my own tools #DIY

#SmallTalk #ObjectPascal #Prolog #Scheme #Racket #CommonLisp #Haskell #Rust #Go #ObjectiveC #Swift

Deploy #LoRa #ReticullumNetwork #RNodes #MeshCore #Meshtastic

Start an #InternetResiliencyClub

Add #Tor, #I2P support by #WebProxy

#SolarPowered #SelfHost over #I2P, #OnionService #Blog #Wiki #Repositories #GopherHole #Darcs #Mercurial

#SelfHost my own #EmailServer, which will only accept email from #KnownServers #CommunityEmail #MutualEmailAcceptance

Share files via #BitTorrent over #I2P

DIY #HomeAutomation
DIY #GardeningAutomation
DIY #GreenHouse

Get a house cat, train the cat, use voice and gestures

Start asking money for advice & technology support

Build/program my own opportunistic and strange cryptocurrency miners #BTC, #XMR, #ZEC, etc #Art

#MakeMoreArt #LearnToDraw #Learn3DModeling #LearnGenerativeArt #LearnToComposeAmbientMusic

#ReCreateJottit #ReCreateInstikiWiki

#WriteMore #PublishMore #Letters, #Essays, #Missives, #Reports, #Treatise

…

#Incomplete#Ongoing#NotFinal
Replied in thread
Jean-Baptiste "JBQ" Quéru

In my little world of #RetroComputing, I have stumbled across minor issues in some of the tools that I use.

I've had two cases so far where maintainers very quickly took my suggestion and made it available in their main branch. I've also had one where I haven't heard back from the maintainer, i.e. where I'm going to need to maintain my own fork (for #RiscV compatibility). And that's OK. Beyond being glad that I got help, I'm glad that the original authors allow me also to do the work myself.

Ertain

The generational leaps I'm seeing with the improvements to #ARM and #RISCV (on SBCs, as well as desktop computer form factors) makes me think of the computer improvements we had in the 90s. This technology almost has that same feel as the progress from 30-some-odd years ago.

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